Power consumption is an important metric in conventional double data rate memory modules. A significant portion of the device power is utilized in the receivers. Power consumption for the memory data-path receivers needs to be significantly reduced. Conventional data-path receivers implement brute force analog (i.e., current mode logic (CML)) signal paths to achieve functionality. More recent efforts in the industry try to use current-steering and/or charge-based summation nodes to achieve a decision feedback equalizer (DFE) function. Similarly, these efforts use CML type stages preceding the DFE to achieve continuous time linear equalizer (CTLE) and variable gain amplifier (VGA) functions.
Power consumption is fundamentally limited by wide input common mode, low-mismatch, low-noise, and high-bandwidth requirements. Additionally, receiver circuitry needs to support fast idle-to-active transitions (i.e., <1 ns). Traditionally analog receiver architectures utilize CML type stages which consumes high power and has tradeoffs between headroom, gain, bandwidth, and power. Charge steering or charge summing topologies still require high-power CTLE and VGA prior to the DFE function. Direct sampling approaches require clock amplification that does not lead to significant phase mismatch between data and clock paths (matched paths between clock and data is a predecessor to charge steering, charge-summing DFEs).
It would be desirable to implement a lower power auto-zeroing receiver incorporating CTLE, VGA, and DFE.